1. Field of the Invention
The invention relates generally to memory systems, and more particularly to systems for increasing the worst-case speed with which memory cells can be read.
2. Related Art
There is a continuing demand in the design of electronic circuits for increased computational power and decreased size and power consumption. These goals are achieved in various ways, such as by improving the physical characteristics of the devices. For example, computational power may be increased by developing components that can operate at higher clock speeds than previous components. Device size may be reduced by using technologies that allow smaller features to be constructed on an integrated circuit die. Lower power consumption may be achieved by using Lower power supply voltages. Many other techniques are also used to meet these demands.
There are, however, physical limitations to some of these techniques. For instance, the frequency and I clock signal used in a digital circuit cannot be increased beyond the point at which the components that use the clock signal become unstable. Similarly, a power supply voltage cannot be reduced to a level at which the components operating on this supply voltage no longer function properly, and the physical size of a circuit components cannot be reduced to a size which is too small to be resolved using available process technologies. It is therefore necessary to find better ways to take advantage of the available technologies.
Once such way of taking advantage of available technologies in the context of memory devices is the use of a hierarchical bit line scheme to read SRAM memory cells. In a conventional system, many SRAM cells (e.g., 128) might be connected to a single, common bit line. Typically, there is a small amount of leakage current between each SRAM cell and the bit line. As a result of the current leaks in all of the cells connected to the bit line, it can be difficult to reliably read data from a single one of the cells. Hierarchical bit line schemes were developed to allow the SRAM cells to be grouped together in smaller numbers so that each cell could be reliably read, despite the leakage from the smaller number of cells.
In a conventional hierarchical bit line scheme, a first group of cells (16, for example) is coupled to a first bit line, while a second group of cells is coupled to a second bit line. Each of the bit lines is input to an evaluation circuit. The outputs of multiple evaluation circuits are then input to further evaluation circuitry. In this manner, a number of cells equivalent to a conventional system (e.g., 128) can be read, even though the cells are grouped into smaller numbers (e.g., 16) on each common bit line.
Even this hierarchical bit line scheme can be improved, however. Because of the physical layout of each SRAM cell, there are certain orientations of the cells that enable optimization of the overall layout of an array of cells. Normally, the cells connected to a particular bit line are arranged in a column. Every second cell in the column can be flipped so that it is a mirror image of the adjacent cells. This allows two adjacent cells to be connected to the bit line at a single junction, which reduces the capacitance of the bit line and thereby increases the speed of the bit line.
As a result of the physical layout of the individual SRAM cells, cells in adjacent columns are flipped with respect to each other, but are not mirror images of each other. Consequently, one column of N cells will have N/2 junctions between the cells and the corresponding common bit line, while the adjacent column of N cells will have N/2+1 junctions between the cells and the common bit line for that column. The columns in an array of memory cells will therefore alternate between N/2 junctions and N/2+1 junctions. Because the alternating bit lines have different numbers of junctions, they will have slightly different capacitances and slightly different speeds. This difference is aggravated by the fact that a typical evaluation circuit based on a NAND gate has one input which is slightly slower than the other. Because all of the memory cells must operate according to the same clock signal, the frequency of this clock signal must be low enough to accommodate the worst case of reading a cell connected to a slower one of the bit lines which is coupled to the slower input of the corresponding evaluation circuit.
It would therefore be desirable to provide systems and methods for reducing these worst case delays.